1. Field of the Invention
The present invention relates to a solid-state imaging device, a method of controlling the solid-state imaging device, and an imaging device.
2. Description of Related Art
In recent years, imaging devices such as video cameras and electronic still cameras have generally come into wide use. Charge coupled device (CCD)-type or amplification-type solid-state imaging devices have been used in such imaging devices (hereinafter referred to as “cameras”). In the amplification-type solid-state imaging devices, a plurality of pixels are arrayed in a matrix form. In the amplification-type solid-state imaging devices, signal charges generated and stored by photoelectric conversion units serving as light-receiving units of pixels are guided toward amplification portions installed in the pixels, and the signals amplified by the amplification portions are output as output signals from the pixels.
Examples of the amplification-type solid-state imaging device include a solid-state imaging device in which a junction field effect transistor is used in an amplification portion and a complementary metal oxide semiconductor (CMOS)-type solid-state imaging device in which a CMOS transistor is used in an amplification portion.
In the past, a general CMOS-type solid-state imaging device (hereinafter, also referred to as a “solid-state imaging device”) has utilized a method of sequentially reading signal charges generated and stored by photoelectric conversion units of pixels arrayed in a two-dimensional matrix form from each row. According to this reading method, an exposure timing in the photoelectric conversion unit of each pixel is determined by start and end of the reading of the signal charge. Therefore, the exposure timing is different in each pixel. Therefore, when a fast moving subject is imaged using such a CMOS-type solid-state imaging device, the subject in the captured image may be distorted.
As an exposure method of eliminating the distortion of the subject, a simultaneous imaging function (hereinafter referred to as a “global shutter function”) of generating signal charges and realizing simultaneity of the storage of the signal charges by exposing all of the pixels at the same timing has been suggested. CMOS-type solid-state imaging devices having the global shutter function tend to be used for many purposes.
In the CMOS-type solid-state imaging devices having the global shutter function, it is generally necessary to store the signal charges generated by the photoelectric conversion units until reading ends. Therefore, a storage capacitor having a light-shielding property is necessary. In the CMOS-type solid-state imaging devices having the global shutter function according to the related art, after simultaneous exposure of all of the pixels, the signal charges generated by the photoelectric conversion units are simultaneously transmitted to the storage capacitors in all of the pixels and are stored once, and then the signal charges stored in the storage capacitors are sequentially converted into pixel signals at a predetermined reading timing.
As a technology for resolving such a problem, for example, Japanese Unexamined Patent Application, First Publication No. 2010-219339 discloses a method of suppressing an increase in a chip area (mounting area) of a solid-state imaging device by separately manufacturing a first substrate in which photoelectric conversion units are formed and a second substrate in which a plurality of MOS transistors are formed and by joining the first and second substrates together to form one solid-state imaging device. According to the technology disclosed in Japanese Unexamined Patent Application, First Publication No. 2010-219339, the separately manufactured first and second substrates are electrically connected to each other by connection electrodes.
According to the technology disclosed in Japanese Unexamined Patent Application, First Publication No. 2010-219339, pixels having the global shutter function according to the related art are distributed between the two substrates. Accordingly, an increase in the chip area of the first substrate can be avoided. By joining the first and second substrates together, it is possible to prevent a signal quality from deteriorating due to noise caused by light during a waiting period until the signal charges stored in the storage capacitors are read.
FIGS. 10A and 10B are diagrams illustrating the overview of a connection configuration of substrates of a solid-state imaging device of the related art to which the technology disclosed in Japanese Unexamined Patent Application, First Publication No. 2010-219339 is applied. FIG. 10A is a side view illustrating the connection configuration of the first and second substrates of a solid-state imaging device 100. FIG. 10B is a top view illustrating the connection configuration of the first and second substrates of the solid-state imaging device 100.
In the solid-state imaging device 100, as shown in FIG. 10A, a pixel unit 11 formed in the first substrate and a pixel unit 12 formed in the second substrate are connected to each other via inter-substrate connector 13. More specifically, photoelectric conversion units are formed in the pixel unit 11 and the storage capacitors are formed in the pixel unit 12. In the inter-substrate connector 13, for example, the photoelectric conversion unit in the pixel unit 11 and the storage capacitor in the pixel unit 12 are connected to each other via a bump. Thus, in the solid-state imaging device 100, the pixel units 11 and 12 connected to each other via the bumps are configured to form a lamination structure in the region of a pixel array unit 40 of the solid-state imaging device 100.
The technology disclosed in Japanese Unexamined Patent Application, First Publication No. 2010-219339 discloses processes (manufacturing processes) of thinning the first substrate and forming color filters or micro-lenses after connecting the first and second substrates to each other. This means that when the chip area of the first substrate is different from that of the second substrate, as shown in FIGS. 10A and 10B, the process of connecting the first and second substrates to each other in units of chips is performed and then the manufacturing processes of thinning the substrate and forming the color filters or the micro-lenses are also performed in units of chips.